By increasing the packing density, VLSI circuits have been scaled down considerably. Unfortunately, the smaller dimensions of the devices are associated with numerous physical phenomena and effects which interfere with the design and operation of these devices. One such phenomena, hot-electron effects, is caused by the ever-increasing channel electric fields in scaled-down devices. The resulting excessive hot-electron substrate current can cause several problems. Most notable are overloading the on-chip substrate-bias generator, variations in threshold voltages, snap-back (avalanche) breakdown in a MOSFET transistor, or latch-up in CMOS circuits. Furthermore, the minority current in the substrate, which is generated by injection from the source substrate junction or by photons emitted from the high electric fields in the drain region of the transistor, can cause DRAM (dynamic random access memory) refresh-time degradation and can discharge other charge-storage or low-current carrying nodes. The threshold shift and transconductance degradation due to interface-state generation by high-energy electrons limits the maximum allowable operating bias and is a major reliability concern.
To relieve these hot-electron induced problems, many graded-drain structures such as offset-gate, double-diffused drain, and lightly-doped-drain (LDD) have been proposed. These structures lower the channel electric field in the device by providing a section of the drain and source with lower density doping. This lower density doping section drops part of the applied voltage and thereby lowers the intensity of the electric field. Unfortunately, the offset-gate structure and the double-diffused drain are not suitable for sub-micron channel-length devices. The lightly-doped-drain (LDD) structure is suitable for sub-micron channel-length devices. However, one or two additional masking steps are required to manufacture such a device in CMOS circuits. If the circuit contains only n-type or only p-type LDD devices, one extra masking step beyond that normally needed to manufacture a VLSI device is required to form the LDD structure. However, if the circuit contains both n-type and p-type LDD devices, then two extra masking steps beyond that normally needed to manufacture a CMOS VLSI circuit is required. This is costly.
This invention presents a new way to achieve the LDD structure in CMOS circuits without using extra masking steps. This new process uses multiple layer side wall spacers similar to those described in a pending patent application entitled Side Wall Masked Isolation For Semiconductor Fabrication, Ser. No. 679,618, incorporated herein by reference. The present invention has a new and completely unanticipated use of side wall spacers. Also, a new process for forming the side wall spacers and the lightly doped regions is presented. In the abovereferenced patent application, a method is disclosed which uses side walls in manufacturing an oxide layer to avoid the formation of the so-called "bird's beak" structure and a few other process- or structure-induced defects. The walls and part of the bottom of a channel are covered with a thin silicon nitride (Si.sub.3 N.sub.4) layer. An oxide is grown in the channels which pushes the thin silicon nitride layer out of the channel and produces smooth walls without the bird's beak structure and other malformations. The thin nitride layer is then removed. The present invention uses side walls to shield regions of the source and drain adjacent to the gate from ion implantation when the source and drain are heavily doped. After these heavily-doped source and drain regions are formed, the side wall spacers are removed with a wet etching process and the newly exposed areas immediately adjacent to the gate are lightly doped. In this manner, a source and a drain with two regions of differing concentrations of doping are formed.